1. Field of the Invention
The invention relates to methods for exploring feasibility of an electronic system design and to electronic systems selected in accordance with such exploration method. The methods in accordance with embodiments of the present invention are particularly suited for electronic systems being fabricated in nanometer technology.
2. Description of the Related Technology
Yield, i.e. the proportion of devices produced which function correctly, can be classified into two different types, functional and parametric yield. Functional yield can be defined as the percentage of samples that produce the correct output for all the possible inputs. Similarly parametric yield can be defined as the percentage of samples that produce the correct output for all the possible inputs under a constraint on one of its performance parameters. Usual constraints are either timing constraints or energy budgets that need to be met.
Process variability in nanometer technology has a detrimental impact on the performance of electronic systems (like or including memories). The impact of process variability on the energy consumption and performance of integrated circuits is significant already now, and is predicted to grow still more as technology scales further. This impact is directly translated into functional and parametric yield loss at the system component level. Although at the component level the parameter variation due to process variability may not be fatal, timing yield loss at the component level may result in functional yield loss at the system level for synchronous systems, due to timing violations.
Conventional yield models do not allow accurately analyzing this, at least not at the system level.
Several approaches exist to turn this functional yield loss at least partly into parametric timing yield loss at the system level, for example by frequency binning at manufacturing-time, as described by M. Mani et al. in “A new statistical optimization algorithm for gate sizing”, Intl. Conf. on Computer Design, pp. 272-277, October 2004. Each chip is tested at-speed after fabrication and the maximum clock frequency it can sustain without loss of functionality is determined. This means that all the system components of the chip, or the respective clock domain, should be operational under this clock frequency for the chip to yield. The system timing parametric yield is defined as the percentage of chips that can run at a given clock frequency. This technique significantly increases the number of chips that are functionally operational, but most of them cannot meet the initial target clock frequency. This is not a problem in the general purpose processor domain, but it will result in application deadline misses for embedded real-time systems, which is one of the reasons why frequency binning is not used in the embedded domain.
Embedded systems that run real-time, power sensitive applications are becoming an important part of the consumer electronic product market. System level design in the embedded systems domain has primarily been concerned with three main cost metrics: timing, energy consumption and area. Timing is important because embedded system typically run applications with hard real-time deadlines, such as communication services and multimedia applications. Minimizing energy consumption, on the other hand, can not only extend the time between battery recharges, but also enables new handheld applications and high-end mobile computing. A lot of research has been performed on how to minimize energy consumption, by employing run-time techniques such as voltage scaling for instance. These two metrics, together with area, which has a direct proportional impact on cost, define the quality of the design.
Estimating both energy and timing parametric yield at the system level during the design trajectory can give valuable information about technical and financial aspects of the design. D. Blaauw et al., in “CAD tools for variation tolerance”, Design Automation Conference, p. 766, 2005, have already identified the lack of yield estimation tools before synthesis and the necessity to have them. Parametric yield is conventionally evaluated on a component per component basis. Currently, system parametric yield is estimated as the product of the parametric yield of all the system components. This leads to a pessimistic worst-case estimation, because it assumes that all the components must meet the same performance requirements. This is an option mostly used in the context of general purpose architecture design, where the processors need to handle any application that is ran on them. The main assumption so far at the system level design abstraction has been that timing and energy consumption of the individual system components and the final system implementation itself are deterministic and predictable.
However, in the portable battery-operated real-time embedded system domain, where the applications that are going to run on the system are known and the most important constraint is meeting the application deadlines and not whether the system components meet their nominal clock period specifications, the system level parametric yield estimation can be significantly improved.
The fact that, for battery-operated systems the utilization scenarios can be predicted at design-time because the applications are known a priori, gives an opportunity to meet the real-time application deadlines, without having to be so strict that all the components have to meet the nominal parametric specifications all of the time. Design techniques exist today that can allow to globally re-decide on the distribution of the available time until the application deadline and on the configuration of the components in order to meet the application deadlines. One of the most prominent techniques is Dynamic Voltage and Frequency Scaling (DVFS), as described by T. Okuma et al. in “Real-time task scheduling for a variable voltage processor”, Intl. Symposium on System Synthesis, pp. 24-29, November 1999. Dynamic Voltage and Frequency Scaling uses the supply voltage as a configuration parameter in order to minimize energy/power consumption and the clock frequency as a constraint to guarantee meeting the application deadlines. Another technique is Vth-hopping, as described by K. Nose et al. in “Vth-hopping scheme to reduce subthreshold leakage for low-power processors”, IEEE J. of Solid-State Circuits, vol. 37, no. 3, pp. 413-419, March 2002, which uses the threshold voltage of the transistors as a configuration parameter. The basic idea behind all these techniques is that the clock frequency will be defined based on the predicted system workload [I. Hong, M. Potkonjak, M. Srivastava, “On-line scheduling of hard real-time tasks on variable voltage processors”, Intl. Conf. on Computer Aided Design, pp. 653-656, November 1998] so as to just meet the next application deadline and a configuration parameter, e.g. Vdd or Vth will be configured in order to minimize energy consumption for the given clock frequency. Other techniques could also be used to optimize the energy-performance trade-offs.
Two important assumptions are supporting the fore-mentioned techniques. The first is that the relation between the configuration parameter and the speed of each component is deterministic and known at design-time. Process variability, however, introduces non-determinism in these relations and jeopardizes the applicability of these techniques. The second assumption is that relaxing the clock frequency does not degrade the parametric yield of the system, because the application deadlines will be met. But, they still use the nominal target clock frequency as the timing reference for the calculation of the system parametric yield. If the slowest system component cannot meet this nominal target, the system is considered as non-functional, because the slow component would cause timing violations. Hence, the conventional parametric yield metrics cannot fully capture the effect of frequency scaling, especially in case the operating frequency is tuned to be faster than the nominal frequency.
Limited variations due to process variability have been tackled by embedding worst-case margins in the design of the system components, such as e.g. processors and memories, so that the specified performance and energy consumption can be guaranteed for use by the system designers.
Technology scaling past the 90 nm technology node, however, introduces a lot more unpredictability in the timing and energy consumption of the designs due to process variability. Treating these metrics at the system design level as deterministic values requires the design margins to become so large that they can cat up all the benefits of moving to a more advanced technology node. Therefore some degree of uncertainty will always have to be tolerated in the component. This has to be considered during circuit and even architecture design. This has to lead to new statistical design paradigms [S. Borkar, “Designing reliable systems from unreliable components: the challenges of transistor variability and degradation”, IEEE Micro, vol. 25, iss. 6, November-December 2005.] such as statistical timing analysis or even more general, yield-aware design [A. Agarwal et al., “Process variation in embedded memories: failure analysis and variation aware architecture” IEEE Journal of Solid-State Circuits, vol 40, iss 9, September 2005 pp. 1804-1814, M. Mani et al, “An efficient algorithm for statistical minimization of total power under timing yield constraints”, Design Automation Conference, 2005.].
Depending on the component being considered (e.g. memory or datapath), energy and/or performance vs. area trade-off decisions have to be made [C. Visweswariah, “Statistical Timing of Digital Integrated Circuits” Microprocessor Circuit Design Forum at ISSCC 2004]. However, for embedded system design the most critical trade-offs are not made at the component or IP block level, but at the architecture or even at the application level. Therefore solutions for (parametric) yield aware design have started being developed that tackle the problem at the architecture level while allowing some degree of uncertainty in the parametric energy and performance figures of the IP blocks [T. Austin et al., “Making typical silicon matter with Razor”, IEEE Computer, pp. 57, March 2004, A. Papanikolaou et al., “A System-Level Methodology for Fully Compensating Process Variability Impact of Memory Organizations in Periodic Applications”, Intl. Conference on HW/SW Co-design and System Synthesis (CODES+ISSS), September 2005]. These solutions aim to tackle the system-level yield loss that is the result of timing violations due to the parametric drift in the performance of the individual system components caused by random process variability.
At the circuit-level, statistical timing analysis has been proposed as a method to analyze the parametric timing yield of the circuits, as described by E. Jacobs et al. in “Gate sizing using a statistical delay models”, Design, Automation and Test in Europe, 2000. A lot of research has been done on analysis of timing yield, for instance by K. Antreich et al. in “Circuit analysis and optimization driven by worst-case distances”, IEEE Trans. on CAD, January 1994, and by A. Srivastava et al. in “Statistical optimization of leakage power considering process variations using dual-Vh and sizing”, Design Automation Conference, June 2004. Lately the focus has been shifted toward optimization of the circuits in order to achieve a larger timing yield, as described by A. Agarwal et al. in “Statistical timing analysis using bounds and selective enumeration”, IEEE Trans. on CAD, vol 22, no. 9, September 2003. Only very recently, statistical timing analysis has been combined with a power optimization methodology based on the allocation of high or low Vth gates in the circuits in order to meet a given timing and minimize power consumption, as described by H. Chang et al. in “Statistical timing analysis considering spatial correlations using a single PERT-like traversal”, Intl. Conf on Computer Aided Design, 2003.
Design for Yield and Design for Manufacturing have become very popular research issues in the recent years. The bulk of the work, however, has been concentrated either at the printing level using post processing techniques or at the standard cell level by characterizing the yield of particular layout styles [J. Yang et al, “Advanced timing analysis based on post-OPC extraction of critical dimensions” DAC, 359-364, 2005.]. Techniques of the fist type such as Optical Proximity Correction aim to counteract the imperfections in the manufacturing process and to increase the device-level functional yield of the chips by improving the quality of the drawn features.
At higher abstraction levels, research has been focused on the gate-level abstraction level of the circuits. Statistical timing analysis [C. Viswewariah, “Death, taxes and failing chips”, Design Automation Conference, pp. 343, 2003.] aims at estimating the parametric performance of the circuit. More recent research has introduced circuit level timing optimizations [A. Srivastava et al, “Concurrent Sizing, Vdd and Vth Assignment for low power design”, DATE, 718-719, 2004.] and combined power and timing optimization [M. Mani et al, “An efficient algorithm for statistical minimization of total power under timing yield constraints”, Design Automation Conference, 2005.] on top of statistical timing analysis.
A gate level approach has been proposed which can accurately estimate the bivariate timing/leakage power distribution of a combinatorial circuit [A. Sriristava et al., “Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance”, Design Automation Conference, pp. 535-540, June 2005]. The correlations between leakage power and performance are taken into account and the resulting joint distribution at the circuit level is generated. The assumption made in this work is that the underlying gate distributions are Gaussian. Such a technique could be properly adapted to handle the yield estimation of a memory organization, if the memory level distributions are assumed to be Gaussian. It cannot handle the case of configurable memories/components, however, or the case of any kind of component with non-Gaussian energy/performance distribution.
The fore-mentioned methods are applicable only at the circuit level, where each circuit is a collection of interconnected logic gates. The methods that perform optimization rely on design-time decisions, such as high-Vth gate allocation and gate sizing. As a result, all of them use the conventional parametric yield metric, which for embedded systems completely ignores the impact of the application that is running and the mapping of that application on the platform. Furthermore, the energy overhead resulting from the design margins introduced at the circuit level to improve parametric yield become prohibitive for battery operated embedded systems.
Parametric yield has not been studied at the application level, especially not for systems that can adapt their clock frequency and energy consumption at run-time. Timing parametric yield can only be defined conventionally for a given timing reference which is assumed to be the clock period.